Intelligent memory architecture

ABSTRACT

An intelligent memory device comprises a data module, an access module and an interface module and is configured to allow data manipulation to take place within the data module without the involvement of the host system. The memory module consists of a plurality of data storage elements each of which has an associated three port switch enabling data communication between the data storage elements without data having to tie up the data bus of the host system. The access module comprises a 1:N switch and a range decoder. The 1:N switch provides access between the host system data bus and the three port switches of the data module, while the range decoder decodes a range of addresses to be affected by an internal memory operation. The interface module comprises an instruction decoder and control logic and is responsive to an instruction sent to the intelligent memory device by the host system to control the operation of internal memory manipulations. Intelligent memory devices can be used to perform a variety of memory data manipulations of varying complexity, including summing, gating, searching and shifting. In the simplest form of intelligent memory device only two operations are provided, these being a shift up and a shift down, each of which causes the data in a range of contiguous memory locations to be shifted by one memory location in the given direction.

1. INTRODUCTION

The present invention relates to improvements in Intelligent MemoryDevices (IMDs). Intelligent Memory Devices are memory devices capable ofperforming other functions independently of the host processor, inaddition to storage of data. Besides standard read and write commands,they might support functions like shifting, adding, and searching ofdata held in their memory.

According to a first aspect, the present invention consists in a memorymodule for storing data, and having a memory array organised as aplurality of contiguous data word storage elements, an access systemarranged to provide a plurality of access modes to the memory array, andan interface system arranged to interpret access requests delivered tothe module via address, data and control lines and to provide controlsignals to the access system to select the required access mode, toprovide address information to select the storage element or elements tobe accessed, and to provide access to the selected storage element orelements, the interface and access systems being arranged to provideconventional read/write access to the memory array in response to aconventional read/write request to the memory module and to provideadditional access modes which allow data to be operated on within thememory module independently of a host system to which the memory moduleis connected.

According to a second aspect the present invention consists in anaddress range decoding device for controlling selection of a range ofaddresses in a storage array, comprising first and second address inputmeans, decoding logic means and a plurality of address selectionoutputs, there being one output for each address in the storage array,the address range decoding means being arranged to accept starting andending address codes as said first and second address inputsrespectively and the decoding logic being arranged to activate thoseoutputs corresponding to the first and second input addresses and eachaddress between the first and second input addresses to facilitate anoperation on the data in the range of storage locations bounded by thestarting and ending addresses.

According to a third aspect the present invention consists in aninstruction decoding device for decoding a memory operation instruction,comprising address input means, read/write control signal input means,instruction decoding logic and one or more outputs arranged to indicatea data operation to which the instruction relates, the instructiondecoding logic being arranged to set the one or more outputs dependingupon relative values of the address and control signals presented to theinput means.

According to a fourth aspect the present invention consists in aninstruction decoding device for decoding an instruction indicating anoperation to be performed on data in a storage array having a pluralityof contiguous addressable storage locations, the device comprising firstand second address input means, read/write control signal input means,instruction decoding logic, address range decoding logic, one or moreinstruction outputs arranged to indicate the operation to be performedand a plurality of address selection outputs, the instruction decodinglogic being arranged to compare the first and second addresses andrespective read/write control signals and to set the one or moreinstruction outputs depending upon the relative values of the addressand control signals, the address range decoding logic being arranged tocontrol the plurality of address selection outputs, there being oneaddress selection output for each address in the storage array, theaddress range decoding logic being arranged to accept starting endending address codes as said first and second address inputs and toactivate those address selection outputs corresponding to the first andsecond input addresses and each address between the first and secondinput addresses to select a range of storage locations bounded by thestarting and ending addresses which contain the data upon which theoperation is to be performed.

In various embodiments of the invention the interface system decodesinformation provided via the address, data and/or control lines of themodule to determine the starting and ending address of the data to beoperated on and the form of operation to be performed.

This may be achieved by writing a predetermined data word to a storagelocation within the address space of the memory module, by performing anaccess to a predetermined address or an address within a predeterminedrange of address, or by a predetermined sequence of control signals.

In a preferred embodiment the operation instruction is indicated by apredetermined sequence of control signals which correspond to a readoperation within the address space of the memory module, followed by awrite operation within the same address space. Preferably, in thisembodiment the ending address of the data to be operated on is given bythe address specified in said read operation and the starting address ofthe data to be operated on is given by the address specified in saidwrite operation.

Preferably, in embodiments of the invention the memory would provideconventional read/write functionality and therefore the read operationof the abovementioned embodiment would be functionally equivalent to aconventional read operation on the memory array and the write operationwould be functionally equivalent to a conventional write operation onthe memory array, but wherein the write operation function would bedelayed until after the data from the storage element at startingaddress had been operated on.

2. BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention will now be described in further detailwith reference to the accompanying drawings in which:

FIG. 1 is a simplified block schematic of a memory system usingIntelligent Memory Architecture;

FIG. 2 is a tree diagram illustrating the relationship of the componentsof Intelligent Memory Architecture;

FIG. 3 is a more detailed block schematic of the system of FIG. 1;

FIG. 4 shows a simplified memory map illustrating the effects of a pushand pull operation in a Range Shifting Memory (RSM);

FIG. 5 is a block schematic illustrating the differences between astandard RAM and a Range Shifting Memory (RSM);

FIGS. 6 and 7 respectively schematically illustrate Back Push-Pull andFront Push-Pull memory systems;

FIG. 8 illustrates different possible memory implementations that can beused for Front or Back Push-Pull memory systems;

FIG. 9 schematically illustrates a data storage element of The RangeShifting Memory;

FIG. 10 schematically illustrates a Range Shifting Memory which makesuse of 3-port RAM devices;

FIG. 11 illustrates a single bit memory element which could be used toimplement a Range Shifting Memory;

FIGS. 12 and 13 show block schematics for a number of Push-Pull memoryconfigurations using two-ported memory devices;

FIGS. 14, 15 and 16 show block schematics for a number of Push-Pullmemory configurations using single ported memory devices;

FIG. 17 illustrates the input and output configuration of a rangedecoder;

FIG. 18 illustrates a truth table for a "two to four" line addressdecoder;

FIG. 19 illustrates a truth table for a "two to four" line rangedecoder;

FIG. 20 illustrates a circuit for implementing a "two to four" rangedecoder which makes use of "two to four" line decoders;

FIG. 21 illustrates a circuit for implementing a "two to four" rangedecoder which uses combinational logic;

FIG. 22 is a block schematic illustrating hardware access usinginstruction registers;

FIG. 23 is a block schematic illustrating hardware access using adistributed hardware interface;

FIGS. 24, 25 and 26 illustrate three methods of Distributed HardwareInterfacing;

FIG. 27 shows several sequential images of a simplified memory map andillustrates how the bidirectional nature of a shift instruction can beused to perform Push and Pull operations;

FIG. 28 shows several sequential images of a simplified memory map andillustrates a Push operation performed with Control lines being used todefine Push operation;

FIG. 29 shows several sequential images of a simplified memory map andillustrates a Pull operation performed with Control lines being used todefine Pull operation;

FIG. 30 illustrates a table listing the event sequences used to controlthe Push and Pull operations illustrated in FIGS. 28 and 29;

FIGS. 31 and 32 illustrate the use of consecutive read and writeinstructions to perform a data shifting as a Push and a Pull operationrespectively;

FIG. 33 illustrates a block schematic diagram of an instruction decoderfor a Control Line Distributed Hardware Interface system;

FIG. 34 is a table illustrating the relationship between relativeaddresses, Operation and Control signal in the Instruction Decoder ofFIG. 33;

FIG. 35 is a truth table of a "two to four" line shift decoder;

FIG. 36 illustrates a combinational logic circuit which implements thetruth table of FIG. 35;

FIGS. 37, 38 and 39 are block schematic diagrams showing methods ofcascading Range Shifting Memory modules.

The invention, Intelligent Memory Architecture (IMA), it allowsIntelligentMemory Devices to be implemented in an efficient manner. Itis consisted ofthree major modules: the Interface Module (IM), theAccess Module (AM) and the Data Module (DM).

Intelligent Memory Architecture provides a standard framework forimplementation of Intelligent Memory Devices. The Interface Module (IM)allows instructions to be issued to the Intelligent Memory Device in amulti-user, multi-tasking environment with minimum overhead. The AccessModule (AM) facilitates the sharing of Intelligent Memory Deviceresourcesby allowing flexible access to specific portions of theIntelligent Memory Device. The Data Module (DM) allows different typesof memory elements to be used in the Intelligent Memory Device.

By using Intelligent Memory Architecture, Intelligent Memory Devices canhave their functionality greatly enhanced through betterhardware/softwareinterface and simplified designs.

3. Intelligent Memory Architecture (IMA)

The block diagram of Intelligent Memory Architecture has a distinctivetopography (see FIG. 1.) in which the storage elements of the DataModule (DM) are interconnected with one another in a loop structure Land are connected to the host via parallel switching structure T of theAccess Module (AM). The Interface Module (IM) controls the data flowaround the loop L of the Data Module and through the parallel structureT of the Access Module. Each of the 3 major modules of a systemincorporating Intelligent Memory Architecture have two sub-components asshown in FIG. 2.

The Interface Module (IM) comprises the Instruction Decoder (ID) and theControl Logic (CL). The Instruction Decoder (ID) is responsible forinterfacing with the host and decoding all the instructions issued bythe host. The Control Logic (CL) gets the result from the InstructionDecoder (ID) to find out what the host wants and controls every thingelse in the Intelligent Memory Architecture to perform the requiredfunction.

The Access Module (AM) comprises the Range Decoder (RD) and the 1:Nswitch (1S). The Range Decoder (RD) is responsible for selecting thecorrect memory banks (M) in FIG. 1.) to operate upon. The 1:N Switch(1S) is a setof parallel switches which control the data paths betweenthe host and the memory banks, allowing the host to access data in allof the memory banks.

The Data Module (DM) comprises Data Storage (DS) and the three PortSwitches (3S). The Data Storage (DS) can be any group of addressablememory elements that can store data; flip-flops, registers, dynamic orstatic RAM, magnetic or optical disks even optical cubes. The selectionofwhich type to use depends on the functions provided by the Intelligentmemory device. The Three Port Switch (3S) is responsible for making theselected type of Data Storage device accessible from the host andadjacentmemory banks independently of the type of storage elements usedin the DataStorage, how many ports the Data Storage has and the natureof those ports.

A block diagram of the above six components and theirinter-relationships is shown in FIG. 3. Note that Intelligent MemoryArchitecture (IMA) only specifies the Instruction Decoder (ID), RangeDecoder (RD) and Three Port Switch (3S) components. The other components(Control Logic (CL), 1:N Switch (1S) and Data Storage (DS)) areapplication specific and should be defined by the designer on a case bycase basis, depending on the value-added functions provided by theparticular Intelligent Memory Device.

The implementation of the value-added functions (operations other thanstandard read and write) for each Intelligent Memory Device isdifferent. By way of example, a novel Intelligent Memory Device known asa Range Shifting Memory (RSM) will be described herein, but theapplication of Intelligent Memory Architecture is not limited to onlythis type of device.

4. Range Shifting Memory (RSM)

The shifting of data in memory is a very frequently performed by asoftwareoperation. Range Shifting Memory provides a "hardware assisted"method of shifting data, by providing two hardware instructions, Pushand Pull. The two instructions, Push(address1, address2) andPull(address1, address2), are supplied with two input addresses each,defining the address range in memory that will be operated upon.

All data items within the range will be moved into the next storagelocation in memory during a Push operation and they will be moved intotheprevious storage location in memory during a Pull operation. As shownin FIG. 4. The Push-Pull operation is similar to that of a shiftregister. But instead of moving bits left and right within a singleword, whole memory words are moved up and down within the memory space.Also unlike a shift register, only specific words, not all words, areshifted at once.

While at first glance it would seem logical that address1 should alwaysbe less than address2 this is not the case. In fact, Push(address1,address2)is equal in function to Pull(address2, address1) and via verse.Thus there is really only a need for one shift instruction, but havingtwo separate Push and Pull instructions is useful in explaining thehi-directional nature of the shifting in the context of linear memoryaddresses.

The aim of the Range Shifting Memory is to shift data, via the Push-Pullinstructions, independently of the host. Each Push-Pull operationconsistsof a sequence of operations to shift data up or down within thememory area. A Push or Pull will be performed depending on the directionof the shift.

Range Shifting Memory is a special type of RAM. Besides standardread/writeaccess to data words in memory, groups of data words in RangeShifting Memory can be shifted to adjacent memory locations very quickly(see FIG. 5.).

5. Push-Pull Methods

The Push-Pull (or shift) operation can be classified as either a Frontor Back Push-Pull operation.

In a Back Push-Pull operation, the shifting operation is performeddirectlyon memory cells after the address decoding circuit (see FIG.6.). This allows shifting of multiple data items concurrently, resultingin very high speeds and would be implemented using devices such asregister based FIFOs and the Am95C85. This form of Push-Pull operationis more suitable for VLSI implementation using Charge-Coupled Devices,shift registers etc.

In Back Push-Pull the address decoder is not used for the Push-Pulloperation and thus this mode of operation is not limited by the conceptoffixed length address locations. Large amounts of data can be moved allat once, resulting in very fast data movement. Existing shift registersor FIFOs are examples of the Back Push-Pull devices. The problem withBack Push-Pull systems is the difficulty in making use of existingmemory devices in their implementation.

With Front Push-Pull systems the operation is performed using theaddress decoding circuit (see FIG. 7.). Data items are normally movedsequentially, one data item at a time, e.g. by the use of the CPU or theDMA controller. The Front Push-Pull form of Range Shifting Memory maymakeuse of readily available RAM chips and could be implemented in VLSIusing standard RAM cells.

In order to perform the Front Push-Pull operation, the decoding circuitis used to read the data from one location and then write the data backto another location in the memory. Existing DMA controllers are anexample ofhardware that uses Front Push-Pull operation. The problem withFront Push-Pull systems is their slow Push-Pull speed.

The Australian Patent Number 627520 describes fast ways of moving dataitems in memory using Front Push-Pull techniques called Split andSegment Push-Pull operations. These two techniques are optimised forFront Push-Pull operation using conventional single-port memory andbuffers. They provide, for the first time, very high speed frontPush-Pull systems.Examples of memory devices that support the twodifferent types of Push-Pull systems are shown in FIG. 8.

6. Using Intelligent Memory Architecture for Range Shifting Memory

Intelligent Memory Architecture takes a front or back Push-Pull memorysystem (like one of those described above) and wraps around it specialsystem interfaces (the Instruction Decoder), decoding logic (the RangeDecoder) and data paths (the 3-port Switch). By encapsulating the frontorback Push-Pull memories, Intelligent Memory Architecture provides anenhanced Push-Pull memory--the Range Shifting Memory.

All of the data in the Range Shifting Memory can be accessed by the hostprocessor as if they are contained in standard RAM. Specific range ofdatawords in Range Shifting Memory can also be selected and shiftedwithout affecting other data.

The block diagram of the Range Shifting Memory is the same as that ofthe Intelligent Memory Architecture (FIG. 1.) and has the same loop andparallel switching data paths. It is made up of the same 3 majormodules: Data (DM), Access (AM) and Interface (IM). Each major moduleagain has thesame two sub-components. (see FIG. 2. and FIG. 3.).

Range Shifting Memory in one broad form provides a method offacilitating data shifting in a computer. It consists of a Data Module(the loop path (L)) for inter-memory bank data transfer, a Access Module(the parallel path (T)) for host access and Interface Module (IM) forinterfacing with the host.

In the Range Shifting Memory, the data records being push-pulled, travelalong the loop path (L) up and down the memory banks (in the DataModule),while the host accesses data records via the parallel path (T)(in the Access Module). Along the loop path, each memory bank (M) haslinks to adjacent banks, thus parallel data transfer is possible. Withthe Range Shifting Memory, the more banks we have, the faster thePush-Pull operation.

Range Shifting Memory has a unified Push-Pull structure that can be usedfor both Front and Back Push-Pull. It increases Push-Pull speed bybreaking the memory up into separate banks and allowing concurrent datatransfer between those banks.

The infrastructure provided by Intelligent Memory Architecture givesRange Shifting Memory the ability to perform different types ofPush-Pulls and to use different data storage elements allows it toprovide more flexible Push-Pulls with increased functionality.

7. Data Module

The Data Module (DM) is made up of memory banks (M) which have threeaccessports. One port is for normal read/write access to the host. Theother two ports are for read/write access to the two adjacent memorybanks respectively. All the memory banks (M) are linked together in aloop (FIG.3.). Each memory bank (M) is made up of a data storage element(DS) and a 3-port switch (3S), as shown in FIG. 9.

The aim of the Data Module is to arrange memory banks into a structurethatcan be accessed easily by the host and also support efficientintelligent memory operations. By linking different Data Storages (DS)into a loop viathe Three Port Switches (3S), it allows information to bepassed between adjacent memory banks concurrently resulting in very highbandwidth.

For many other Intelligent Memory Devices, the Three Port Switch (3S)will perform much more than just switching, there can be an arithmeticcircuit inside for addition, for example. But in the case of RangeShifting Memorythe Three Port Switch only performs switching. Thus RangeShifting Memory is one of the most basic of all Intelligent MemoryDevices built with Intelligent Memory Architecture, and can be used asthe platform for development of other Intelligent Memory Devices.

The Data Storage (DS) component of memory banks M determines whether theRange Shifting Memory is to implement a Front or Back Push-Pulloperation.If there is an address decoding circuit residing inside DataStorage (DS), then the Range Shifting Memory implements a FrontPush-Pull. The memory banks are then made up of random access memory(RAM), where we can access individual memory cells by their addresses.

If there is no address decoding circuit inside Data Storage, then theRangeShifting Memory implements a Back Push-Pull operation. The memorybanks arethen made up of registers, where all the memory cells in theData Storage (DS) are accessed as a group. We can separately accessindividual memory cells within Data Storage, by way of the decodingcircuit in the Access Module (AM).

The Three Port Switch (3S) is responsible for making all different typesofData Storage (DS) accessible from the host and adjacent memory banksindependent of how many ports the Data Storage (DS) has and the natureof those ports.

The memory banks (M) (comprising Data Storage and Three Port Switch),can be implemented in many different ways including simple CMOStransmission gates, single transistor dynamic RAM cells, six transistorstatic RAM cells, flip-flops, external RAM chips, charge coupleddevices, magnetic disks or optical cubes.

We can implement the Front Push-Pull Range Shifting Memory usingtriple-port (3-port) RAM in the memory bank M, as shown in FIG. 10. ThePush-Pull logic circuit controls the address and read/write lines of thetwo "Up and Down" ports of the 3-port RAM so to provide Push-Pullfunctionality, and the host controls the remaining port for normalread/write operation. In this case, the Three Port Switch is built intoand is part of the 3-port RAM, and there is no need for a separate ThreePort Switch.

The Front Push-Pull action is achieved by the control logic setting theaddress lines of the 3-port RAMs and toggling the read/write lines. So,ina push down operation, each of the up ports in the 3-port RAM will beset to receive data from the down port immediately above.

If the Range Shifting Memory needs to supply a total capacity of 2Kwords by 8 bits, then with 64 banks (M), each 3-port RAM requires acapacity of 32 by 8. In this case, the word size of the 64 3-port RAMbanks is the same as that of the memory banks (M). Note that the RAMword size can be smaller, in which case we then simply cascade moreRange Shifting Memorys in parallel to achieve bigger Range ShiftingMemory word size.

For Back Push-Pull operation, each memory bank (M), can be implementedwitha Push-Pull register that is made up of a plurality of single bitdevices similar to that shown in FIG. 11. The single bit device of FIG.11 is built with a multiplexer feeding data into a D flip-flop. ThePush-Pull logic controls the CTL and CLK signals to facilitate thePush-Pull operation.

The Back Push-Pull action is achieved by the control logic setting theCTL signals and toggling the CLK signals. So, in a push down operation,all ofthe CTL signals will be set such that data at the input linetaking a signal from above will be passed to the input port of the Dflip-flop and then the CLK line is toggled to store that data.

The number of these one bit devices required depends on the word size ofthe Push-Pull register, if we have 8-bit Push-Pull registers then 8 ofthose one bit devices are needed for each register. Since each Push-Pullregister equates to one memory element M, the number of memory elementsina Range Shifting Memory is the same as the number of Push-Pullregisters. If the Range Shifting Memory needs to supply a total capacityof 2K words by 8 bits, then we need 2K banks, that is 2K of 8-bitPush-Pull registers.In this case, the Three Port Switch is the 4 to 1multiplexer in front of the D flip-flop.

Besides the existence and non-existence of decoding circuits (for Frontor Back Push-Pull devices), there are other differences between one typeof Data Storage and another, like number of ports, whether there areseparateI/O connections and whether the Data Storage devices supportconcurrent read/write to the same location etc. The Data Storage (DS)being used in FIG. 10. has three bi-directional ports, while the DataStorage (DS) used in FIG. 11. has a single port with separate I/O.

A distinctive feature of the Data Module (DM) when used as a Push-Pullstructure is that it allows loopback, thus items in the bottom bank canbepushed back to the top bank and items in the top bank can be pulledinto the bottom bank. This loopback feature is vital in Split andSegment Push-Pull operations where standard RAM banks are used as DataStorage devices as it allows communication between the top and bottombanks and thus enables the Push-Pull action to be performed on data setsthat have more data items than the number of banks.

7.1 Data Module Implementation

FIG. 12 shows two examples of implementation of the Data Module usingdual-port Data Storages (DS) with switches (S). The switches (S), aresimple on-off devices that either pass the data or block it. CMOStransmission gates or tri-state transceivers can be used to implementthe switches (S). FIG. 13 shows two examples which use crossbars (X)instead of switches. These crossbars can selectively link any of theirports together at one time. However, the crossbars are quite expensive,and multiplexers can be used to emulate their function.

FIG. 14 shows two examples of implementations of the Data Module LoopStructure and Access Modules (Three Port Switch and 1:N Switch) usingsingle port Data Storages (DS) with switches (S). Note that theright-handexample requires less switches but has reduced host accessperformance. FIG. 15 shows two examples using crossbars (X) instead ofswitches. Note that the right-hand example uses Data Storage (DS)elements with separate I/O instead of hi-directional I/O. The Three PortSwitch (3S) in this embodiment is similar to the Three Port Switch inFIG. 11. since they eachhave to support single-port Data Storage (DS)with separate I/Os.

Another variation using single port Data Storage (DS) with separate I/Ois shown in FIG. 16. In this embodiment each Three Port Switch (3S) isdivided into two parts S1 and S2. During host access both S1 and S2 areclosed, during Push-Pull operation one is open the other is closed, thiseffectively creates two loops for Push-Pull data to pass along dependingon whether a Push or a Pull operation is being performed.

Buffers can be added to the Three Port Switch (3S) to improve operation.They can be used to hold data temporarily during their travel betweenDataStorages (DS), which is useful when the Data Storage has a limitednumber of ports or when the Data Storage doesn't support concurrentaccess from multiple ports to the same memory location. The Split andSegment Push-Pull technique described in Australian Patent Number 627520is based on the use of buffers in Front Push-Pull modules.

There can be other further variations to the Range Shifting Memory. Formemory with more than three ports, we can implement Range ShiftingMemoryswith multiple memory loops L or multiple host access (3S), thusallowing multiple Push-Pulls and hosts accesses to occur concurrently.Also, if thenumber of memory bank (M) is equal to the number of words inthe Range Shifting Memory, then the Data Module becomes a linear path,because thereis no need for loop back. But the basic philosophy andcomponents, with theThree Port Switches (3S) and Data Storages (DS),remained the same.

8. Access Module

In order to support the multi-user and multi-tasking environments, a wayofcontrolling the access to the memory banks in the Data Module (DM) isrequired. Since most memories have linear addresses, a way of selectingaddress ranges by hardware will allow very efficient access to groups ofmemory banks in the Data Module.

The Access Module (AM) allows the host (via the Interface Module) toaccessthe Data Module (DM). It performs address decoding and dataswitching, and is made up of a 1:N Switch (1S) and a Range Decoder (RD).(see FIG. 2. andFIG. 3.)

8.1. Range Decoder

Decoding is the central part of Intelligent Memory Architecture, and infact this is one of the features that sets it apart from other memoryhardware. The decoding makes the Intelligent Memory Device look likestandard RAM to the host processor thus making it very easy to use andmanage. It also allows multiple Intelligent Memory Devices to becascaded together to provide wider words or more words.

In order for the Access Module (AM) to be implemented effectively, anovel Range Decoder (RD) is used for the purpose of selecting a specificrange of data items in memory. The Range Decoder (RD) has two sets ofinputs andone set of outputs (FIG. 17.). The begin address (A) and theend address (B) are applied to the two sets of inputs respectively andall of the outputs that are between those two address will be selected(S). In the binary case, if the addresses are n bits wide then therewill be 2n inputs(for the 2 addresses) and 2^(n) =m outputs. The rest ofthis specification will use the binary range decoder as an example, butthe scope of the invention should not be limited to this embodiment.

The range decoder is a super-set of the standard line decoder. Ratherthan selecting a specific line that corresponds to the value of oneinput code (as in 2 to 4 line decoders), the range decoder selects allof the lines between the values of two input codes (a 2 to 4 rangedecoder has the samenumber of outputs, 4, as the line decoder but has 4inputs rather than 2).

The truth tables of a 2 to 4 line decoder and 2 to 4 range decoder areshown in FIG. 18. and FIG. 19. respectively. Note that if the two inputvalues are the same then the range decoder becomes a normal linedecoder.

The more memory banks (M) in the Data Module (DM), the larger the rangedecoder needs to be. If we have 64 banks then we need a 6 to 64 rangedecoder. The range decoder can be implemented with hardwiredcombinationallogic or using a ROM table or with comparators. FIG. 20.shows a serial combinational logic partial implementation of a 2 to 4range decoder, while FIG. 21. shows a parallel combinational logic fullimplementation ofa 2 to 4 range decoder.

With the range decoder, the Access Module has the ability to select anyuser-defined continuous range of address after being given the beginaddress and end address of the range.

8.2 1:N Switch

The 1:N Switch (1S) in the Access Module (AM) is used to concentrate thedata from the large number of Three Port Switches (3S), so that the hostcan access the Data Storage (DS) in a transparent manner. It switchesthe single data bus from the host between the memory banks (M) in theData Module (DM). If there are 64 Memory Banks in the Data Module thenwe need a 1:64 switch. The 1:N Switch can be built using multiplexers,crossbars or simply a tristate bus with enable pins on each memory bank(M).

In the case of FIG. 10., the 1:N Switch is built into the 3-port RAM,sincethe 3-port RAM supports tri-state buses. In case of FIG. 11., the1:N Switch is not shown, but it can be implemented with wired-or gates,tri-state buffers or multiplexers.

9. Interface Module

The high data transfer speed of the Range Shifting Memory is availableto the host through the Interface Module (IM). All Interface Modules ofIntelligent Memory Architecture use an novel hardware/software interfacecalled Distributed Hardware Interface (DHI). A Distributed HardwareInterface overcomes a lot of the problems experienced by currenthardware/software interfaces. Although a Distributed Hardware Interfaceisillustrated with Range Shifting Memory here, it can be used by otherIntelligent Memory Devices for improved hardware/software interfacing aswell.

Most software accesses hardware via a set of instruction registers. Theregisters are mapped into a single fixed set of memory addresses thatare shared by all applications. A layer of software must be added abovethe hardware to manage the shared address space, as shown in FIG. 22.This software approach, although commonly used, is very complex, slow,non-scaleable and non-portable.

To avoid problems associated with such software "device driver" schemes,a Distributed Hardware Interface allows the Range Shifting Memory to beutilised without the need of special management software. Theinstructionsto Range Shifting Memory are distributed in the sense thatall applicationshave assigned to them their own Range Shifting Memoryaddress space (where protection is enforced transparently by theprocessor's own memory management system) and the instructions theyissue in that address space will only apply to data items in the sameaddress space.(FIG. 23.)

Rather than having separate instruction or command pins on the hardwarepackage, a Distributed Hardware Interface is implemented by using thestandard pins on memory packages: the address pins, the data pins andthe control pins (such as chip select and read/write). Programs issuecommandsby standard read/writes to their allocated memory range.

Most instructions or commands have two parts, the opcode and theoperand. The opcode indicates the action to be performed while theoperand indicates what the action is to be performed on. In aDistributed HardwareInterface both opcode and operand must berepresented using standard address, data and control signals that areavailable on standard memory devices such as a static RAM chip.

9.1. Types of DHI

One type of Distributed Hardware Interface, termed Address DHI, is showninFIG. 24. where the memory space allocated to each application isdivided into instruction (I) and data (D) space. Within the instructionaddress space, the value of the memory address indicates the specificopcode, while the value of the read/write data to that address is theoperand for that opcode.

To perform the operation Push(address1, address2) we write the requiredoperands, address1 and address2, into the appropriate instructionaddresses. This scheme is called Address DHI, because different opcodesare identified by the different addresses they have in memory. Asindicated before, only the one instruction, like the Push instruction,is needed because of its ability to perform Pull operation when address2and address1 are reversed. However we have shown the Pull instruction aswell,to demonstrate how the scheme works.

Another form of Distributed Hardware Interface is Data DHI. It reversestherole of address and data in Address DHI. The address is now used toindicate the operand while the data is used to indicate the opcode, asshown in FIG. 25. Each application still has its own address space, butthere is no instruction space any more, only data space. A speciallyassigned data value is now used to indicate the opcode. Thus there aresome data values that the applications cannot use, as they have aspecial meaning to the Distributed Hardware Interface.

A special data value that will not be used by the applications, sayFFFF, will be assigned as an opcode. To perform Push(address1,address2), FFFF is written to address1, but rather than writing over thetop of the original data stored in address1), FFFF indicates to theRange Shifting Memory (RSM) that a Push(address1, address2) operation isabout to begin and address1 is one of the operands. The address of thenext write will betaken as address2, thus the Push(address1, address2)operation can start immediately after that write.

Yet another type of Distributed Hardware Interface is Control DHI, wheredifferent opcodes are identified by the control signals (likeread/write) supplied to Range Shifting Memory. The address pins and/orthe data pins can be used to supply the operand.

An embodiment which uses the address pins to supply the operands wouldoperate as follows. To perform the operation Push(address1, address2), aread is performed at address1. The next write to address2 will start thePush(address1, address2) operation. Thus the addresses of all readoperations are constantly stored as address1 and when the first writecomes along, that address will be used as address2 to perform thePush(address1, address2) operation (see FIG. 26.). This scheme onlysupports a small number of opcodes but is adequate for simple devicessuchas Range Shifting Memory.

9.2 Control DHI for Range Shifting Memory

Besides standard read/write access to data words in memory, groups ofdata words in Range Shifting Memory can be Push-Pulled to adjacentmemory locations. Thus Range Shifting Memory supports the followingoperations:

Read(address, data)--read data from address, equivalent to standard readfrom RAM.

Write(address, data)--write data to address, equivalent to standardwrite to RAM.

Shift(address1, address2)--shifts all the data words between address1and address2, from address2 towards address1. This shift operationimplements both a pull up (address1<address2) and a push down(address1>address2). (see FIG. 27.) Note that the memory contents ofaddress1 always get destroyed by the shift, while the contents ofaddress2 always get duplicated.

Using a Distributed Hardware Interface, Range Shifting Memory has noexplicit shift instructions. Programs issue shift commands by standardread/writes to their allocated memory range. This is possible byincorporating the Shift(address1, address2) operation into theRead(address1, data) and Write(address2, data) operations. The firstshiftaddress (address1) is supplied through a read access and the secondshift address (address2) is supplied through the following write access.The shift operation is thus always make up of a read access followed bya write access. All of the data words between the write address(address2) and the previous read address (address1) are shifted oneposition from thewrite address towards the read address.

The host processor performs standard read/write cycle to Range ShiftingMemory as if it is normal RAM. The read cycle, Read(address1, data), isexactly the same as that of normal RAM. An address (address1) issupplied to Range Shifting Memory and a data word from that address isretrieved. The write cycle, Write(address2, data), is slightly differentin that before writing the data word (data) into the given address(address2), theshifting from address2 towards address1 will occur. Afterthe shift the data word (data) is then written into the write address(address2).

In FIG. 28. a push down from address 1 to address 5 is shown. ARead(5,f) operation is followed immediately by a Write(1, x) operation,this is similar to an operation sequence that consists of a Read(5,f)followed by a Shift(5, 1) followed by a Write(1, x). The actual shiftingoperation is thus the first part of the Write operation.

FIG. 29. shows a pull up from address 5 to address 1. The Read(1,b)operation is followed immediately by a Write(5, y) operation. A registerinside Range Shifting Memory keeps track of the last read address (1),when the next write to address 5 occurs, the shifting operation Shift(1,5) beings. The write address (5) and the last read address (1) togetherdefined the address range in Range Shifting Memory, that data is to beshifted, and the direction of the shift. Finally, the value y is writteninto address 5, just as in normal write cycle.

The "shifting" operation is thus "implied" through standard memoryread/writes. By removing the need of a separate Shift operation, RangeShifting Memory software is simplified substantially and Range ShiftingMemory hardware interfaces with any processor and memory systems easily.FIG. 30. summarizes the possible access sequences and the actualoperations.

Since the Control DHI uses sequence sensitive operations, in amultitaskingenvironment, the read and write instructions need to bepackaged one after the other into one operation so that the InterfaceModule will not get confused by some other application doing read orwrites to it in between.

Some computers do not support this type of operation packaging and mightnot have other forms of support for semaphores, but almost all of themsupport the single operation data exchange instruction. That is, thedata value of a memory location and a processor register can beexchanged in a single operation, thus read and write can be performed tothe same addressin one single operation. The exchange instructionguarantees that a write will follow immediately after a read to the sameaddress. To make use of the exchange instruction, a slight modificationof the above Control DHI can be used.

The address1 of the Shift(address1, address2) instruction is obtained bytracking all read operations. If a read from address1 is followedimmediately by a write to (the same) address1 then the data written toaddress1 is taken as address 2. The Shift(address1, address2) operationisthen performed. Note that with the new Control DHI address 1 issupplied via the address pins while address 2 is supplied via the datapins.

FIG. 31. shows the exchange of content of address 5 (which contains avalueof f) with content of a register (which contains a value of 1).Thus the single exchange instruction implements a Shift(5,1) operation.FIG. 32. shows the exchange of content of address 1 (which contains avalue of b) with content of a register (which contains a value of 5).Thus the single exchange instruction implements a Shift(1,5) operation.

9.3 Implementation of Interface Module

In some systems, a combination of the 3 Distributed Hardware Interfaceschemes can be used and further variations can be introduced by makingtheopcodes sequence sensitive (like the Control DHI described above). Sothe same opcode can represent different instructions depending onoperations that have occurred before it.

Different Distributed Hardware Interface schemes are useful in differentsituations, but all schemes are implemented by the Interface Modulewhich is make up of the same two components: a Instruction Decoder (ID)that latches the address, data and control signals, and then decodesthem; and the Control Logic (CL) that takes the decoded result andcontrols the restof the Intelligent Memory Device.

FIG. 33. shows the block diagram of an efficient Instruction Decoderimplementation that is opcode sequence sensitive. Registers are used tolatch the opcodes and operands from the address, data and control bus. Abuffer is available to store previous states of the registers so thecomparator can be used to compare its value with those in the registers.The state machine then change to the appropriate state depending on thevalues in the registers and the result of the comparator.

The other component of the interface module, the Control Logic, ishighly application specific and can be implemented with standard logicdesign techniques, like state machines, and will not be discussedfurther in thisspecification.

10. Range Shifting Memory Implementations

Implementing Range Shifting Memory in integrated circuits is veryefficient. These Range Shifting Memory chips can be built with gatearrays, standard cells or full custom designs. For low capacity designseven FPGAs can be used. Since, like Intelligent Memory Architecture,RangeShifting Memory is a concept, and its realisation can take a numberof forms.

Range Shifting Memory chips can be used directly in building of newcomputers or they can be used in form of memory plug-in boards orco-processors for existing computers. Range Shifting Memory is mappedintothe physical address space of the host processor.

10.1. Shift Decoder

An important function of the Access Module is to control the 3-portSwitches (3S). The Three Port Switches have to be "told" which way topassdata. Using Control DHI, we supply two addresses to the RangeShifting Memory, a read address (A) and a write address (B). If the readaddress isgreater than the write address (A>B), then we have a Pushoperation. If theread address is less than the write address (A<B), thenwe have a pull operation.

FIG. 34. gives an example of the possible signals generated for theThree Port Switches, depending of the read-write addresses supplied. Forexample, these signals can be used as the control signal (CTL) for themultiplexer in FIG. 11.

Since, like the range decoder, these Three Port Switch control signalsrequire the read address (A) and the write address (B) as inputs. We cancombine the ability to generate these signals into a Range Decode (RD)to form a Shift Decoder (SD). The truth table of a 2 to 4 Shift Decoderis shown in FIG. 35.

The Shift Decoder (SD), takes the read and write addresses, and producesthe required signals to drive all of the Three Port Switches (3S). Aparallel implementation of a 2 to 4 shift decoder is shown in FIG. 36.Note that there are 8 outputs rather than 4, because although thedecoder supplies signals to four Three Port Switches (3S), each ThreePort Switch requires 2 bits of control information (C0 and C1).

10.2. Cascading Range Shifting Memorys

Range Shifting Memory chips can be cascaded together to support largerdatawords (memory width) or more data words (memory depth). RangeShifting Memory cascading is similar to RAM horizontal (data path) andvertical (address path) cascading. Extra address decoding circuits (likeRange Decoders or Shifts Decoders) have to be added to control themultiple chips.

Increasing memory width (horizontal cascading) is quite straight forwardsince there is no communication between Range Shifting Memory chips.Increasing memory depth (vertical cascading) is more complex. If a dataset crosses chip address boundaries, then during a Push-Pull operation,data must be moved from one chip to the next. This can be performedeitherby software or hardware.

The Distributed Hardware Interface is well suited to the softwareapproach.Using the two overlapped "read-write" sequences, one on eachchip, data is transferred between the chips. The read step gathers datafrom one chip while supplying its shift address and the write stepdeposits the data into the next chip while supplying its shift address.The data path remains quite simple, as shown in FIG. 37.

The hardware approach varies from a simple external controller thatissues the two "read-write" sequences instead of the CPU (FIG. 38.) toextra dedicated data buses and logic on each Range Shifting Memory chipfor moving data crossing chip boundaries (FIG. 39.).

We can form a hierarchy of Range Shifting Memorys. The Range ShiftingMemorys can be constructed on circuit boards with Range Shifting Memorychips themselves. Each Range Shifting Memory chip acts like anindividual memory bank (M), with the other components (like AccessModule and Interface Module) provided by external logic on the circuitboard. And thecircuit boards themselves can be treated as memory banks(M) supported by other external logic to form a very big Range ShiftingMemory that is built up of smaller ones.

Cascading of Range Shifting Memory chips also allows Multiple SpeedPush-Pull. That is the Range Shifting Memory chips can run at adifferent clock speed to the inter-chip data transfer. Data items canmove within chips at 100 MHz between the memory banks and move betweenchips at 50 MHz. This is because data can be transferred much fasterwithin the chip than between chips.

The principles of Split and Segment Push-Pull operations can be appliedhere. For example, Memory banks (M) can be grouped together to formblocks, with each block using a Segment Push-Pull operation to transferdata within itself. Between blocks, a Split Push-Pull operation can beused. If the blocks are on different chips then the Split Push-Pulloperation can effectively speed-match between the Push-Pull operationswithin the chip and across the chip address boundary.

11. Conclusion

With the simple interface provided by Intelligent Memory Architectures,Range Shifting Memory applications can be developed under existingoperating systems using standard compilers. Intelligent MemoryArchitecture also provides Range Shifting Memory with a very fast datatransfer rate via the multiple banks in the Data Module. The InterfaceModule makes that speed readily available to multiple applications, withlow overhead. While the Access Module allows different applications toshare Range Shifting Memory easily.

Using Intelligent Memory Architecture's unique design, Range ShiftingMemory differs from other data moving hardware techniques in thefollowingfunctional ways:

(1) It is based on a word address scheme. Where data bits are groupedinto fixed length words that can be moved and accessed as one entity andnot asan arbitrary number of bits.

(2) The data words are accessed individually by the host through linearnumerical addresses, just like that of standard RAM.

(3) Its capacity is measured by "the number of bits per word by thenumber of words" e.g. 2K words by 8 bits. Same as standard RAM.

(4) It can be easily cascaded together with other Range Shifting Memoryto form larger word size or to supply more words. Again, like standardRAM.

(5) With the 3-port switch (Three Port Switch), a large number ofdifferentmemory types can be used for data storage; allowing speed,capacity, cost and design trade offs.

(6) With the range decoder (RD), data words are moved by range, and notas a whole. Data words can be identified in user defined groups and thuscan be shifted without affecting other data words in the Range ShiftingMemory.

(7) Using a Distributed Hardware Interface, Range Shifting Memoryprovides a very efficient data shifting interface with software inmulti-user, multi-tasking environments.

It will be appreciated by persons skilled in the art that numerousvariations and/or modifications may be made to the invention as shown inthe specific embodiments without departing from the spirit or scope oftheinvention as broadly described. The present embodiments are,therefore, to be considered in all respects as illustrative and notrestrictive.

I claim:
 1. A memory module for storing data, and having a memory arrayorganized as a plurality of contiguous memory banks, each memory bankhaving a plurality of data storage elements and three external datapaths respectively communicating with two adjacent memory banks and witha host computer, the module having an access system arranged to providea plurality of access modes to the memory array, one of said modesincluding concurrent selection and activation of multiple memory, banksbetween two given addresses, and an interface system arranged tointerpret access requests delivered to the module via address, data andcontrol lines and to provide control signals to the access system toselect the required access mode, to provide address information toselect the storage element or elements to be accessed within an addressspace of the array, and to provide access to the selected storageelement or elements, the interface and access systems being arranged toprovide conventional read/write access to the memory array in responseto a conventional read/write request to the memory module and to provideadditional access modes which allow data to be operated on within thememory module independently of a system to which the memory module isconnected, the interface system being arranged to decode informationprovided via the address, data and/or control lines of the module duringa conventional read or write operation to the address space of thememory array to determine the begin and end address of the data to beoperated on and the form of a data operation to be performed.
 2. Thememory module of claim 1 wherein an operation instruction directing theinterface system to perform the data operation is indicated to theinterface system by writing a predetermined data word to a storagelocation within the address space of the memory module.
 3. The memorymodule of claim 1 wherein an operation instruction directing theinterface to perform the data operation is indicated to the interfacesystem by performing an access to a predetermined address or an addresswithin a predetermined range of address.
 4. The memory module of claim 1wherein an operation instruction directing the interface to perform thedata operation is indicated to the interface system by a predeterminedsequence of control signals.
 5. The memory module of claim 4 wherein thepredetermined sequence of control signals correspond to a read operationwithin the address space of the memory module, followed by a writeoperation within the same address space.
 6. The memory module of claim 4wherein the begin and end addresses of the data to be operated on areprovided on the address lines of the module.
 7. The memory module ofclaim 6 wherein the end address of the data to be operated on is givenby the address specified in said read operation and the begin address ofthe data to be operated on is given by the address specified in saidwrite operation.
 8. The memory module of claim 7 wherein the readoperation is functionally equivalent to a conventional read operation onthe memory array and the write operation is functionally equivalent to aconventional write operation on the memory array, but wherein the writefunction is delayed until after the data from the storage element at thebegin address has been operated on.
 9. The memory module of claim 4wherein the begin and end addresses of the data to be operated on areprovided on the address and data lines of the module.
 10. The memorymodule of claim 9 wherein the end address of the data to be operated onis given by the address specified in said read operation and thestarting address of the data to be operated on is given by the dataspecified in said write operation.
 11. The memory module of claim 10wherein the interface system includes address range decoding means,comprising first and second address input means, decoding logic meansand a plurality of address selection outputs, there being one output foreach address in the storage array, the address range decoding meansbeing arranged to accept begin and end address codes as said first andsecond address inputs respectively and the decoding logic being arrangedto activate those outputs corresponding to the first and second inputaddresses and each address between the first and second input addressesto facilitate operating on the data in the range of storage locationsbounded by the begin and end addresses.
 12. The memory module of claim11 wherein the interface system includes an instruction decodercomprising first and second address input means, instruction decodinglogic and at least one output arranged to indicate the operationinstruction, the instruction decoding logic being arranged to comparethe first and second addresses and to set the output depending upontheir relative values.
 13. The memory module of claim 8 wherein theinterface system includes address range decoding means, comprising firstand second address input means, decoding logic means and a plurality ofaddress selection outputs, there being one output for each address inthe storage array, the address range decoding means being arranged toaccept begin and end address codes as said first and second addressinputs respectively and the decoding logic being arranged to activatethose outputs corresponding to the first and second input addresses andeach address between the first and second input addresses to facilitateoperating on the data in the range of storage locations bounded by thebegin and end addresses.
 14. The memory module of claim 13 wherein theinterface system includes an instruction decoder comprising first andsecond address input means, instruction decoding logic and at least oneoutput arranged to indicate the operation instruction, the instructiondecoding logic being arranged to compare the first and second addressesand to set the output depending upon their relative values.
 15. Thememory module of claim 14 wherein the address range decoding logic isincorporated into the instruction decoding logic and the instructiondecoder provides at least two output bits for each storage location inthe memory array, to select the location as one to be operated on and toindicate the operation to be performed.
 16. The memory module of claim13 wherein the decoding logic comprises a programmed ROM.
 17. The memorymodule of claim 13 wherein the decoding logic comprises a set of rangeselection outputs, a pair of line decoding circuits and combinationallogic, the decoding circuits and combinational logic providing signalsto the range selection outputs.
 18. The memory module of claim 13wherein the decoding logic comprises a combinational logic circuit. 19.The memory module of claim 15 wherein the decoding logic comprises aprogrammed ROM.
 20. The memory module of claim 15 wherein the decodinglogic comprises a pair of line decoding circuits and combinational logicto derive range selection outputs.
 21. The memory module of claim 15wherein the decoding logic comprises a combinational logic circuit. 22.The memory module of claim 1 wherein the operation to be performed onthe data is a shifting of data from one storage location to anotherwithin the memory array.
 23. The memory module of claim 22 wherein theshifting operation is performed on one or more contiguous storageelements.
 24. The memory module of claim 23 wherein the shiftingoperation is arranged to shift the data in each of the one or morecontiguous storage elements to an adjacent storage element in a givendirection.
 25. The memory module of claim 24 wherein the interfacesystem decodes information provided via the address, data and/or controllines of the module to determine the begin and end address of the datato be shifted and the direction of the shift.
 26. The memory module ofclaim 25 wherein the shift instruction is indicated to the interfacesystem by a predetermined sequence of control signals.
 27. The memorymodule of claim 26 wherein the predetermined sequence of control signalscorrespond to a read operation within the address space of the memorymodule, followed by a write operation within the same address space. 28.The memory module of claim 27 wherein the begin and end addresses of thedata to be operated on by the shift operation are provided on theaddress lines of the module.
 29. The memory module of claim 28 whereinthe end address of the data to be shifted is given by the addressspecified in said read operation and the begin address the data to beshifted is given by the address specified in said write operation. 30.The memory module of claim 29 wherein the read operation is functionallyequivalent to a conventional read operation on the memory array and thewrite operation is functionally equivalent to a conventional writeoperation on file memory array, but wherein the write function isdelayed until after the data from the storage element at the beginaddress has been shifted to the adjacent location.
 31. The memory moduleof claim 27 wherein the begin and end addresses of the data to beoperated on by the shift operation are provided on the address and datalines of the module.
 32. The memory module of claim 31 wherein the endaddress of the data to be shifted is given by the address specified insaid read operation and the begin address of the data to be shifted isgiven by the data specified in said write operation.
 33. The memorymodule of claim 32 wherein the interface system includes address rangedecoding means, comprising first and second address input means,decoding logic means and a plurality of address selection outputs, therebeing one output for each address in the storage array, the addressrange decoding means being arranged to accept begin and end addresscodes as said first and second address inputs respectively and thedecoding logic being arranged to activate those outputs corresponding tothe first and second input addresses to facilitate shifting the data inthe range of storage locations bounded by the begin and end addresses.34. The memory module of claim 33 wherein direction of shifting isdetermined by the relative magnitudes of the first and second address.35. The memory module of claim 30 wherein the interface system includesaddress range decoding means, comprising first and second address inputmeans, decoding logic means and a plurality of address selectionoutputs, there being one output for each address in the storage array,the address range decoding means being arranged to accept begin and endaddress codes as said first and second address inputs respectively andthe decoding logic being arranged to activate those outputscorresponding to the first and second input addresses and each addressbetween the first and second input addresses to facilitate shifting thedata in the range of storage locations bounded by the begin and endaddress.
 36. The memory module of claim 35 wherein direction of shiftingis determined by the relative magnitudes of the first and secondaddress.
 37. The memory module of claim 35 wherein the interface systemincludes an instruction decoder comprising first and second addressinput means, instruction decoding logic and at least one output arrangedto indicate shift direction, the instruction decoding logic beingarranged to compare the first and second addresses and to set the outputdepending upon their relative values.
 38. The memory module of claim 37wherein the address range decoding logic is incorporated into theinstruction decoding logic and the instruction decoder provides a twobit output for each storage location in the memory array, to select thelocation when it is to be shifted and to indicate the shift direction.39. The memory module of claim 36 wherein the decoding logic comprises aprogrammed ROM.
 40. The memory module of claim 35 wherein the decodinglogic comprises a set of range of selection outputs, a pair of linedecoding circuits and combinational logic, the line decoding circuitsand combinational logic providing signals to the range selectionoutputs.
 41. The memory module of claim 36 wherein the decoding logiccomprises a combinational logic circuit.
 42. The memory module of claim38 wherein the decoding logic comprises a programmed ROM.
 43. The memorymodule of claim 38 wherein the decoding logic comprises a set of rangeselection outputs, a pair of line decoding circuits and combinationallogic, the line decoding circuits and combinational logic providingsignals to the range selection outputs.
 44. The memory module of claim38 wherein the decoding logic comprises a combinational logic circuit.45. An instruction decoding device for decoding an instructionindicating an operation to be performed on data in a storage arrayhaving a plurality of contiguous addressable storage locations, thedevice comprising first and second address input means, read/writecontrol signal input means, instruction decoding logic, address rangedecoding logic, one or more instruction outputs arranged to indicate theoperation to be performed and a plurality of address selection outputs,the instruction decoding logic being arranged to compare the first andsecond addresses and respective read/write control signals and to setthe one or more instruction outputs depending upon the relative valuesof the address and control signals, the address range decoding logicbeing arranged to control the plurality of address selection outputs,there being one address selection output for each address in the storagearray, the address range decoding logic being arranged to accept beginand end address codes as said first and second address inputs and toactivate those address selection outputs corresponding to the first andsecond input addresses and each address between the first and secondinput addresses to select a range of storage locations bounded by thebegin and end addresses which contain the data upon which the operationis to be performed.
 46. The memory module of claim 45 wherein thedecoding logic comprises a programmed ROM.
 47. The memory module ofclaim 45 wherein the decoding logic comprises a set of range selectionoutputs, a pair of line decoding circuits and combinational logic, theline decoding circuits and combinational logic providing signals to therange selection outputs.
 48. The memory module of claim 45 wherein thedecoding logic comprises a combinational logic circuit.